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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">FPSCR, Floating-Point Status and Control Register</h1><p>The FPSCR characteristics are:</p><h2>Purpose</h2>
        <p>Provides floating-point system status information and control.</p>
      <h2>Configuration</h2><p>AArch32 System register FPSCR bits [31:27] are architecturally mapped to AArch64 System register <a href="AArch64-fpsr.html">FPSR[31:27]</a>.</p><p>AArch32 System register FPSCR bit [7] is architecturally mapped to AArch64 System register <a href="AArch64-fpsr.html">FPSR[7]</a>.</p><p>AArch32 System register FPSCR bits [4:0] are architecturally mapped to AArch64 System register <a href="AArch64-fpsr.html">FPSR[4:0]</a>.</p><p>AArch32 System register FPSCR bits [26:15] are architecturally mapped to AArch64 System register <a href="AArch64-fpcr.html">FPCR[26:15]</a>.</p><p>AArch32 System register FPSCR bits [12:8] are architecturally mapped to AArch64 System register <a href="AArch64-fpcr.html">FPCR[12:8]</a>.</p><p>This register is present only when AArch32 is supported. Otherwise, direct accesses to FPSCR are <span class="arm-defined-word">UNDEFINED</span>.</p>
        <p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether the Len and Stride fields can be programmed to nonzero values, which will cause some AArch32 floating-point instruction encodings to be <span class="arm-defined-word">UNDEFINED</span>, or whether these fields are RAZ.</p>

      
        <p>Implemented only if the implementation includes the Advanced SIMD and floating-point functionality.</p>
      <h2>Attributes</h2>
        <p>FPSCR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">N</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_30">Z</a></td><td class="lr" colspan="1"><a href="#fieldset_0-29_29">C</a></td><td class="lr" colspan="1"><a href="#fieldset_0-28_28">V</a></td><td class="lr" colspan="1"><a href="#fieldset_0-27_27">QC</a></td><td class="lr" colspan="1"><a href="#fieldset_0-26_26">AHP</a></td><td class="lr" colspan="1"><a href="#fieldset_0-25_25">DN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-24_24">FZ</a></td><td class="lr" colspan="2"><a href="#fieldset_0-23_22">RMode</a></td><td class="lr" colspan="2"><a href="#fieldset_0-21_20">Stride</a></td><td class="lr" colspan="1"><a href="#fieldset_0-19_19-1">FZ16</a></td><td class="lr" colspan="3"><a href="#fieldset_0-18_16">Len</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15">IDE</a></td><td class="lr" colspan="2"><a href="#fieldset_0-14_13">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-12_12">IXE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-11_11">UFE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-10_10">OFE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9">DZE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8">IOE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_7">IDC</a></td><td class="lr" colspan="2"><a href="#fieldset_0-6_5">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4">IXC</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3">UFC</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">OFC</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1">DZC</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">IOC</a></td></tr></tbody></table><h4 id="fieldset_0-31_31">N, bit [31]</h4><div class="field">
      <p>Negative condition flag. This is updated by floating-point comparison operations.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-30_30">Z, bit [30]</h4><div class="field">
      <p>Zero condition flag. This is updated by floating-point comparison operations.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-29_29">C, bit [29]</h4><div class="field">
      <p>Carry condition flag. This is updated by floating-point comparison operations.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-28_28">V, bit [28]</h4><div class="field">
      <p>Overflow condition flag. This is updated by floating-point comparison operations.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-27_27">QC, bit [27]</h4><div class="field">
      <p>Cumulative saturation bit, Advanced SIMD only. This bit is set to 1 to indicate that an Advanced SIMD integer operation has saturated since 0 was last written to this bit.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-26_26">AHP, bit [26]</h4><div class="field">
      <p>Alternative half-precision control bit:</p>
    <table class="valuetable"><tr><th>AHP</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>IEEE half-precision format selected.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Alternative half-precision format selected.</p>
        </td></tr></table><p>This bit is used only for conversions between half-precision floating-point and other floating-point formats.</p>
<p>The data-processing instructions added as part of the <span class="xref">FEAT_FP16</span> extension always use the IEEE half-precision format, and ignore the value of this bit.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-25_25">DN, bit [25]</h4><div class="field">
      <p>Default NaN mode control bit:</p>
    <table class="valuetable"><tr><th>DN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>NaN operands propagate through to the output of a floating-point operation.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Any operation involving one or more NaNs returns the Default NaN.</p>
        </td></tr></table>
      <p>The value of this bit controls only scalar floating-point arithmetic. Advanced SIMD arithmetic always uses the Default NaN setting, regardless of the value of the DN bit.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-24_24">FZ, bit [24]</h4><div class="field">
      <p>Flush-to-zero mode control bit:</p>
    <table class="valuetable"><tr><th>FZ</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Flush-to-zero mode enabled.</p>
        </td></tr></table><p>The value of this bit controls only scalar floating-point arithmetic. Advanced SIMD arithmetic always uses the Flush-to-zero setting, regardless of the value of the FZ bit.</p>
<p>This bit has no effect on half-precision calculations.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-23_22">RMode, bits [23:22]</h4><div class="field">
      <p>Rounding Mode control field. The encoding of this field is:</p>
    <table class="valuetable"><tr><th>RMode</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Round to Nearest (RN) mode.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Round towards Plus Infinity (RP) mode.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Round towards Minus Infinity (RM) mode.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>Round towards Zero (RZ) mode.</p>
        </td></tr></table>
      <p>The specified rounding mode is used by almost all scalar floating-point instructions. Advanced SIMD arithmetic always uses the Round to Nearest setting, regardless of the value of the RMode bits.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-21_20">Stride, bits [21:20]</h4><div class="field"><p>If this field is RW and is set to a value other than zero, some floating-point instruction encodings are <span class="arm-defined-word">UNDEFINED</span>. The instruction pseudocode identifies these instructions.</p>
<p>Arm strongly recommends that software never sets this field to a value other than zero.</p>
<p>The value of this field is ignored when processing Advanced SIMD instructions.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>When an implementation implements FPSCR.LEN,STRIDE as RAZ, access to this field is <span class="access_level">RAZ/WI</span>.</p></div><h4 id="fieldset_0-19_19-1">FZ16, bit [19]<span class="condition"><br/>When FEAT_FP16 is implemented:
                        </span></h4><div class="field">
      <p>Flush-to-zero mode control bit on half-precision data-processing instructions:</p>
    <table class="valuetable"><tr><th>FZ16</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Flush-to-zero mode enabled.</p>
        </td></tr></table>
      <p>The value of this bit applies to both scalar and Advanced SIMD floating-point half-precision calculations.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-19_19-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-18_16">Len, bits [18:16]</h4><div class="field"><p>If this field is RW and is set to a value other than zero, some floating-point instruction encodings are <span class="arm-defined-word">UNDEFINED</span>. The instruction pseudocode identifies these instructions.</p>
<p>Arm strongly recommends that software never sets this field to a value other than zero.</p>
<p>The value of this field is ignored when processing Advanced SIMD instructions.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>When an implementation implements FPSCR.LEN,STRIDE as RAZ, access to this field is <span class="access_level">RAZ/WI</span>.</p></div><h4 id="fieldset_0-15_15">IDE, bit [15]</h4><div class="field">
      <p>Input Denormal floating-point exception trap enable.</p>
    <table class="valuetable"><tr><th>IDE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Untrapped exception handling selected. If the floating-point exception occurs, the IDC bit is set to 1.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the IDC bit.</p>
        </td></tr></table>
      <p>When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>When an implementation does not implement trapping of Input Denormal floating-point exceptions, access to this field is <span class="access_level">RAZ/WI</span>.</p></div><h4 id="fieldset_0-14_13">Bits [14:13]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-12_12">IXE, bit [12]</h4><div class="field">
      <p>Inexact floating-point exception trap enable.</p>
    <table class="valuetable"><tr><th>IXE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Untrapped exception handling selected. If the floating-point exception occurs, the IXC bit is set to 1.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the IXC bit.</p>
        </td></tr></table>
      <p>When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>When an implementation does not implement trapping of Inexact floating-point exceptions, access to this field is <span class="access_level">RAZ/WI</span>.</p></div><h4 id="fieldset_0-11_11">UFE, bit [11]</h4><div class="field">
      <p>Underflow floating-point exception trap enable.</p>
    <table class="valuetable"><tr><th>UFE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Untrapped exception handling selected. If the floating-point exception occurs, the UFC bit is set to 1.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Trapped exception handling selected. If the floating-point exception occurs and Flush-to-zero is not enabled, the PE does not update the UFC bit.</p>
        </td></tr></table>
      <p>When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>When an implementation does not implement trapping of Underflow floating-point exceptions, access to this field is <span class="access_level">RAZ/WI</span>.</p></div><h4 id="fieldset_0-10_10">OFE, bit [10]</h4><div class="field">
      <p>Overflow floating-point exception trap enable.</p>
    <table class="valuetable"><tr><th>OFE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Untrapped exception handling selected. If the floating-point exception occurs, the OFC bit is set to 1.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the OFC bit.</p>
        </td></tr></table>
      <p>When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>When an implementation does not implement trapping of Overflow floating-point exceptions, access to this field is <span class="access_level">RAZ/WI</span>.</p></div><h4 id="fieldset_0-9_9">DZE, bit [9]</h4><div class="field">
      <p>Divide by Zero floating-point exception trap enable.</p>
    <table class="valuetable"><tr><th>DZE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Untrapped exception handling selected. If the floating-point exception occurs, the DZC bit is set to 1.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the DZC bit.</p>
        </td></tr></table>
      <p>When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>When an implementation does not implement trapping of Divide by Zero floating-point exceptions, access to this field is <span class="access_level">RAZ/WI</span>.</p></div><h4 id="fieldset_0-8_8">IOE, bit [8]</h4><div class="field">
      <p>Invalid Operation floating-point exception trap enable.</p>
    <table class="valuetable"><tr><th>IOE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Untrapped exception handling selected. If the floating-point exception occurs, the IOC bit is set to 1.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the IOC bit.</p>
        </td></tr></table>
      <p>When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>When an implementation does not implement trapping of Invalid Operation floating-point exceptions, access to this field is <span class="access_level">RAZ/WI</span>.</p></div><h4 id="fieldset_0-7_7">IDC, bit [7]</h4><div class="field"><p>Input Denormal cumulative floating-point exception bit. This bit is set to 1 to indicate that the Input Denormal floating-point exception has occurred since 0 was last written to this bit.</p>
<p>How VFP instructions update this bit depends on the value of the IDE bit.</p>
<p>Advanced SIMD instructions set this bit if the Input Denormal floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, regardless of the value of the IDE bit.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-6_5">Bits [6:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_4">IXC, bit [4]</h4><div class="field"><p>Inexact cumulative floating-point exception bit. This bit is set to 1 to indicate that the Inexact floating-point exception has occurred since 0 was last written to this bit.</p>
<p>How VFP instructions update this bit depends on the value of the IXE bit.</p>
<p>Advanced SIMD instructions set this bit if the Inexact floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, regardless of the value of the IXE bit.</p>
<p>The criteria for the Inexact floating-point exception to occur are different in Flush-to-zero mode. For more information, see <span class="xref">'Flush-to-zero'</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-3_3">UFC, bit [3]</h4><div class="field"><p>Underflow cumulative floating-point exception bit. This bit is set to 1 to indicate that the Underflow floating-point exception has occurred since 0 was last written to this bit.</p>
<p>How VFP instructions update this bit depends on the value of the UFE bit.</p>
<p>Advanced SIMD instructions set this bit if the Underflow floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, if FPSCR.UFE is 0 or if Flush-to-zero is enabled.</p>
<p>The criteria for the Underflow floating-point exception to occur are different in Flush-to-zero mode. For more information, see <span class="xref">'Flush-to-zero'</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-2_2">OFC, bit [2]</h4><div class="field"><p>Overflow cumulative floating-point exception bit. This bit is set to 1 to indicate that the Overflow floating-point exception has occurred since 0 was last written to this bit.</p>
<p>How VFP instructions update this bit depends on the value of the OFE bit.</p>
<p>Advanced SIMD instructions set this bit if the Overflow floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, regardless of the value of the OFE bit.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-1_1">DZC, bit [1]</h4><div class="field"><p>Divide by Zero cumulative floating-point exception bit. This bit is set to 1 to indicate that the Divide by Zero floating-point exception has occurred since 0 was last written to this bit.</p>
<p>How VFP instructions update this bit depends on the value of the DZE bit.</p>
<p>Advanced SIMD instructions set this bit if the Divide by Zero floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, regardless of the value of the DZE bit.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-0_0">IOC, bit [0]</h4><div class="field"><p>Invalid Operation cumulative floating-point exception bit. This bit is set to 1 to indicate that the Invalid Operation floating-point exception has occurred since 0 was last written to this bit.</p>
<p>How VFP instructions update this bit depends on the value of the IOE bit.</p>
<p>Advanced SIMD instructions set this bit if the Invalid Operation floating-point exception occurs in one or more of the floating-point calculations performed by the instruction, regardless of the value of the IOE bit.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="access_mechanisms"><h2>Accessing FPSCR</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">VMRS{&lt;c&gt;}{&lt;q&gt;} &lt;Rt&gt;, &lt;spec_reg&gt;</h4><table class="access_instructions"><tr><th>reg</th></tr><tr><td>0b0001</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif !ELUsingAArch32(EL1) &amp;&amp; !(EL2Enabled() &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; == '11') &amp;&amp; CPACR_EL1.FPEN != '11' then
        if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.AArch32SystemAccessTrap(EL2, 0x00);
        else
            AArch64.AArch32SystemAccessTrap(EL1, 0x07);
    elsif ELUsingAArch32(EL1) &amp;&amp; ((ELUsingAArch32(EL3) &amp;&amp; SCR.NS == '1' &amp;&amp; NSACR.cp10 == '0') || CPACR.cp10 == '0x') then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; == '11' &amp;&amp; CPTR_EL2.FPEN != '11' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.E2H == '1' &amp;&amp; CPTR_EL2.FPEN == 'x0' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.E2H != '1' &amp;&amp; CPTR_EL2.TFP == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL1) &amp;&amp; ((ELUsingAArch32(EL3) &amp;&amp; SCR.NS == '1' &amp;&amp; NSACR.cp10 == '0') || HCPTR.TCP10 == '1') then
        AArch32.TakeHypTrapException(0x08);
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x07);
    else
        R[t] = FPSCR;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif CPACR_EL1.FPEN == 'x0' then
        AArch64.AArch32SystemAccessTrap(EL1, 0x07);
    elsif (ELUsingAArch32(EL3) &amp;&amp; SCR.NS == '1' &amp;&amp; NSACR.cp10 == '0') || CPACR.cp10 == '00' then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.E2H != '1' &amp;&amp; CPTR_EL2.TFP == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.E2H == '1' &amp;&amp; CPTR_EL2.FPEN == 'x0' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; ((ELUsingAArch32(EL3) &amp;&amp; SCR.NS == '1' &amp;&amp; NSACR.cp10 == '0') || HCPTR.TCP10 == '1') then
        AArch32.TakeHypTrapException(0x08);
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x07);
    else
        R[t] = FPSCR;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; ((ELUsingAArch32(EL3) &amp;&amp; SCR.NS == '1' &amp;&amp; NSACR.cp10 == '0') || HCPTR.TCP10 == '1') then
        AArch32.TakeHypTrapException(0x00);
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x07);
    else
        R[t] = FPSCR;
elsif PSTATE.EL == EL3 then
    if CPACR.cp10 == '00' then
        UNDEFINED;
    else
        R[t] = FPSCR;
                </p><h4 class="assembler">VMSR{&lt;c&gt;}{&lt;q&gt;} &lt;spec_reg&gt;, &lt;Rt&gt;</h4><table class="access_instructions"><tr><th>reg</th></tr><tr><td>0b0001</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif !ELUsingAArch32(EL1) &amp;&amp; !(EL2Enabled() &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; == '11') &amp;&amp; CPACR_EL1.FPEN != '11' then
        if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.AArch32SystemAccessTrap(EL2, 0x00);
        else
            AArch64.AArch32SystemAccessTrap(EL1, 0x07);
    elsif ELUsingAArch32(EL1) &amp;&amp; ((ELUsingAArch32(EL3) &amp;&amp; SCR.NS == '1' &amp;&amp; NSACR.cp10 == '0') || CPACR.cp10 == '0x') then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; == '11' &amp;&amp; CPTR_EL2.FPEN != '11' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.E2H == '1' &amp;&amp; CPTR_EL2.FPEN == 'x0' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.E2H != '1' &amp;&amp; CPTR_EL2.TFP == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL1) &amp;&amp; ((ELUsingAArch32(EL3) &amp;&amp; SCR.NS == '1' &amp;&amp; NSACR.cp10 == '0') || HCPTR.TCP10 == '1') then
        AArch32.TakeHypTrapException(0x08);
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x07);
    else
        FPSCR = R[t];
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif CPACR_EL1.FPEN == 'x0' then
        AArch64.AArch32SystemAccessTrap(EL1, 0x07);
    elsif (ELUsingAArch32(EL3) &amp;&amp; SCR.NS == '1' &amp;&amp; NSACR.cp10 == '0') || CPACR.cp10 == '00' then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.E2H != '1' &amp;&amp; CPTR_EL2.TFP == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.E2H == '1' &amp;&amp; CPTR_EL2.FPEN == 'x0' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; ((ELUsingAArch32(EL3) &amp;&amp; SCR.NS == '1' &amp;&amp; NSACR.cp10 == '0') || HCPTR.TCP10 == '1') then
        AArch32.TakeHypTrapException(0x08);
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x07);
    else
        FPSCR = R[t];
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; ((ELUsingAArch32(EL3) &amp;&amp; SCR.NS == '1' &amp;&amp; NSACR.cp10 == '0') || HCPTR.TCP10 == '1') then
        AArch32.TakeHypTrapException(0x00);
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TFP == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x07);
    else
        FPSCR = R[t];
elsif PSTATE.EL == EL3 then
    if CPACR.cp10 == '00' then
        UNDEFINED;
    else
        FPSCR = R[t];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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